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AD6679 outputs only 7 out of 14 bits

Question asked by ihmig on Apr 21, 2016
Latest reply on May 20, 2016 by ihmig



I'm trying to reproduce the performance characteristics from the datasheet, but unfortunately get a much worse SNR (around 40dB) for a sine input.

What I noticed: When running AD6679 in "Full Bandwidth Mode" (reg 0x220 = 0), the lower 7 data lines (D0..D6) are always zero, only D7..D13 are toggling.

This looks to me as if the ADC inside the AD6679 is not 14 bits as stated in "General Description" in the datasheet, but only 7 bit. Also, when I set a User Test pattern, the lower 7 bits always return as zero (probed at the FMC pins), no matter to which value the bits are set.


I'm using AD6679-EVB on ADS7-V2EBZ with VisualAnalog and SPIController.


Is there a specific register setting which I am missing?


Thank you and best regards,
Matthias Ihmig