As discussed here : Data format ; am trying to send [real+imaginary]samples from FPGA to one of the AD9364,
then send it out and receive it at other AD9364, which is then analysed at the FPGA level using ILA.
Input is a repetition of a single value 64 times(depth) i.e. [ 1000100010 + 10001000100 i ] (Binary) or [222+444i] (hex).
The signals that is being captured by ILA doesn't have same sample magnitude as that of the input, which is obvious because of various path losses involved.
Since, 64 samples are continuously sent out.. there has to be a continuous repetition after certain samples based on the debug clk; & as per my knowledge: these [repetition] samples received should have same phase even if it doesn't have same magnitude, which am not able to identify looking at the output samples.
Can you please take a look at the output samples attached & suggest next step.