AnsweredAssumed Answered

ADSP-21469 dual core layout + external memory

Question asked by diego.zallocco on Jul 13, 2011
Latest reply on Jul 18, 2011 by RChary

Hi all,

I'm planning to use a dual core layout (two ADSP-21469 linked together via LinkPort) in my next project (a multi-channel after market audio processor).

Now I use two ADSP-21469 EZ-board where one dsp (MASTER) is attached to codec, the other one (SLAVE) is used by the first as a co-processor. Data buffers are exchanged between the two dsp through linkport.

My question concerns external memory: can I connect a shared external memory (SDRAM or DDR2) with both dsp?

 

Down here I quote an excerpt of the .LDF file I use in my project:

 

...

 

$OBJECTSA = 21469_hdr.doj, sru_P0.doj, isr.doj, sport.doj, spi.doj, AD1939.doj, pll_ddr2_dram.doj, linkport_P0.doj, main_P0.doj;
$OBJECTSB = 21469_hdr.doj, sru_P1.doj, pll_ddr2_dram.doj, linkport_P1.doj, main_P1.doj;
MEMORY
{
     seg_rth { TYPE(PM RAM) START(0x0008C000) END(0x0008C0FF) WIDTH(48) }
     seg_init { TYPE(PM RAM) START(0x0008C100) END(0x0008C2FF) WIDTH(48) }
     seg_int_code { TYPE(SW RAM) START(0x00124900) END(0x0013BFFF) WIDTH(16) }
     seg_dmda { TYPE(DM RAM) START(0x000B2000) END(0x000BBFFF) WIDTH(32) }
     seg_stak { TYPE(DM RAM) START(0x000BC000) END(0x000BDFFF) WIDTH(32) }
     seg_pmda { TYPE(PM RAM) START(0x000C0000) END(0x000C7FFF) WIDTH(32) }
     seg_heap { TYPE(DM RAM) START(0x000E0000) END(0x000E7FFF) WIDTH(32) }
     // ---------------------------------------------------------------------------
     // SDRAM (one memory for each dsp...)
     // ---------------------------------------------------------------------------
     seg_ddr2_code { TYPE(PM RAM) START(0x0200000) LENGTH(0x3FFF) WIDTH(16) }
     seg_ddr2_data { TYPE(DM RAM) START(0x0306000) LENGTH(0x3FFF) WIDTH(16) }
}
PROCESSOR P0
{
     OUTPUT($COMMAND_LINE_OUTPUT_DIRECTORY\P0.dxe)
     SECTIONS
     {
          seg_rth PM
          {
               NO_FORCE_CONTIGUITY
               INPUT_SECTIONS($OBJECTSA(seg_rth) $LIBRARIES(seg_rth))
          } > seg_rth
          ...
     } /* SECTIONS */
} /* PROCESSOR P0 */
PROCESSOR P1
{  
     OUTPUT($COMMAND_LINE_OUTPUT_DIRECTORY\P1.dxe)
     SECTIONS
     {
          seg_rth PM
          {
               NO_FORCE_CONTIGUITY
               INPUT_SECTIONS($OBJECTSB(seg_rth) $LIBRARIES(seg_rth))
          } > seg_rth
          ...
     } /* SECTIONS */
} /* PROCESSOR P1 */

 

 

MEMORY section is one for all the processors, so the SDRAM addressing is to be intended as one memory IC for every dsp... I'm right?

I tryed to follow implementations suggested in EE-148, but I suppose it's not appliable to the ADSP-21469.

 

Thanks for any suggestion,

Diego

Outcomes