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AD9680 SYSREF Status in Control Bits

Question asked by adiup on Apr 18, 2016
Latest reply on Apr 18, 2016 by UmeshJ

To Whom it May Concern,

 

I am having an issue getting the status of the SYSREF signal to show up in the 2 Control Bits (CS) in the AD9680 data stream. Here is the problem statement:

 

I have a problem on the AD9680 that I would like to get your help with. I have set up the AD9680 for 14-bits of data and 2 control bits. I have also set the device so that the control bits give me SYSREF indications but the control bits received by my FPGA are always "00". The register settings are:

0x58F = 0x8D
0x559 = 0x50 (I also tried 0x55)
0x55A = 0x05

 

This looks correct. Any help here in setting of the device correctly would be greatly appreciated.

 

From the AD9680 Datasheet:

 

By default in the AD9680, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF±, or fast detect output.

 

0x58F = 0x8D
1000 1101

Number of control bits (CS) per sample
00 = no control bits (CS = 0)
01 = 1 control bit (CS = 1); Control Bit 2 only
10 = 2 control bits (CS = 2); Control Bit 2 and 1 only
11 = 3 control bits (CS = 3); all control bits (2, 1, 0)

0x559 = 0x50 (I also tried 0x55)
0101 0000

Converter control Bit 1 selection
000 = tie low (1’b0) 001 = overrange bit
011 = fast detect (FD) bit
101 = SYSREF± Only used when CS (Register 0x58F) = 2 or 3

Converter control Bit 0 selection
000 = tie low (1’b0) 001 = overrange bit
011 = fast detect (FD) bit
101 = SYSREF± Only used when CS (Register 0x58F) = 3

0x55A = 0x05
0000 0101

Converter control Bit 2 selection
000 = tie low (1’b0) 001 = overrange bit
011 = fast detect (FD) bit
101 = SYSREF Used when CS (Register 0x58F) = 1, 2, or 3

 

Thank you,

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