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HDL Reference Designs with Vivado 2016.1

Question asked by on Apr 18, 2016
Latest reply on Apr 18, 2016 by AdrianC



I am trying to use the HDL reference designs with Xilinx Vivado 2016.1 (FMCOMMS2 + ZedBoard in particular).


The selected git branch is "hdl_2016_r1".

The libraries build fine but not the projects: I am getting messages of erroneous ranges in the memory mappings when trying to run the .tcl files. I also changed xilinx clk_wiz block version from 5.2 to 5.3 in zed_system_bd.tcl to reach that point in the first place.


I am not sure if I missed something but I am guessing that the branch is still very recent and the necessary changes have not been made.


Is Vivado 2016.1 a supported version, or will it be soon? Any other suggestions?


Thank you in advance