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PN monitors of the FPGA in the project hdl-hdl_2014_r2

Question asked by angleIsDancing on Apr 18, 2016
Latest reply on May 9, 2016 by rejeesh

Hi all,

  To tuning digital interface, it needs to test the PRBS data received from AD9361 chip in the FPGA and the function is implemented in file "axi_ad9361_rx_pnmon.v". In the "device specific" part of the file, when variable "adc_pn_oos" equals to 0, the FPGA uses the old value of variable "adc_pn0_data_pn" to produce the new value of variable "adc_pn0_data_pn", but when variable "adc_pn_oos" equals to 1, the FPGA uses the value of varialbe "adc_pn0_data_in" (which is the data the FPGA received from AD9361 chip last time)to produce the value of variable "adc_pn0_data_pn". Then

the FPGA matchs the variable "adc_pn0_data_pn" to the variable "adc_pn0_data_in" (the latest data)for the PRBS testing in the file "ad_pnmon.v".  And the value of variable "adc_pn_oos" is produced in the file "ad_pnmon.v".


my questions are:

1.what does variable "adc_pn_oos" equals to 1(or 0) mean? I.e.,what does "out of synchronization"(or not) mean?

2.why the file "ad_pnmon.v" produces the value of variable "adc_pn_oos" using the algorithm implemented in the part "pn oos and counters " ?

3.when testing a PRBS, if for some parts of the PRBS, the result of  match is true; for some other parts, the result of match is false. How to decide whether the  testing is passed or not.