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ADAU1772 48KHz processing by underclocking?

Question asked by JPOV on Apr 14, 2016
Latest reply on Jun 2, 2016 by JPOV

I have some questions regarding sample/clock rates in the ADAU1772 with the goal of processing audio at a 48KHz sample rate and connecting bi-directional audio on the serial port as a slave at 48KHz, 16KHz, and 8KHz (need to support multiple modes of operation) , with a 12.288 MHz ext clock source.  Note we need to run our signal processing 48KHz because at 96KHz there are not enough instruction elements to handle our filter spans which would be twice as long at 96KHz.

 

1. It seems the CORE_FS can only be set for 96KHz or 192KHz (In Register 9) similarly the A/D rate can be set to 96KHz or 192 in Reg 0x1b.

If the A/D rate and  CORE_FS are set to 96KHz can I safely under-clock and setup the clock control so that the master clock and core clock are 6.144MHz (running at 1/2 rate using the divide by 2 in CC_MDIV and CC_CDIV in Reg 0  with the 12.288MHz ext clock) to achieve a  48KHz processing sample rate?   Are there any internal analog filters that won’t automatically adjust with the under-clocking?

 

2. For the serial audio connection, in our setup the ADAU will be the slave (using external serial clk input). In this mode, is the serial clock rate setting  (SER_PORT_FS) in Reg 0x32 used by the chip or totally ignored? Is it still used internally for selection of  decimation/interpolation filters or will these be selected automatically based on a serial clock input rate lock?  Does it have to be set to be “close” to the input serial clock?

 

3.  Assuming SER_PORT_FS does still need to be set as a serial slave and assuming I can underclock at ½ rate then, similarly to question 1) then can you confirm, for example, that if the CORE_FS  and A/D rate are  set to 96KHz and the MCLK is 6.144MHz (underclocked) then if the actual serial input clock was 8KHz then I would need to set SER_PORT_FS to 16KHz to compensate for the underclocking and everything will work out properly (there are no fixed analog filtering effects)?

 

4. Given my setup/goals are there performance optimizations possible by setting CC_MDIV and differently (do I need to under-clock both to achieve my goal)?

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