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[Streaming]: Problem with multiple AXI_DMAC_REG_START_TRANSFER

Question asked by keklaquoi on Apr 14, 2016
Latest reply on Jun 3, 2016 by keklaquoi

Hi everyone,

 

As I told in a previous post, I've got some issues with the DMA of my application. The goal is to transfer images, videos and cam contents from a transmitter (TX) to a receiver (RX).

 

The cyclic mode of the DMA is not enable. Right now, I'm just a the beggining of the development, and I'm trying to send a picture in one time and receive it in 2 times. Here is the code that I am using for the RX part:

 

AnalogDevicePNG.png

If I refer to this page (FPGA Reference Designs: PCORE Register Map [Analog Devices Wiki] ), the  AXI_DMAC_REG_START_TRANSFER should get back to 0 after a transfer is queued, which means, I should be able to queued multiple transfers...

 

0x102     0x0408     TRANSFER_START     AXI DMA Controller

        [0]     TRANSFER_START     RW     Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been successfully queued or the DMA is channel is disabled. Writing a 0 to this register has no effect.

 

I don't know why, but I had to comment the second "while loop", the AXI_DMAC_REG_START_TRANSFER never comes back to 0 for the second transmission, can you help me on this point ?

 

SECOND POINT:

 

After Starting the 2 transfers, I call the function "Check Transfert" twice , to verify that transfers has been done and received properly. Here is the function (it is mostly inspired from what I found on internet, but I had to modify it due to some problem with the TCP connection):

 

AnalogDevice_CheckTransfertPNG.png

 

The first time I call the function, I received the data properly, but my system always crashes the second time I call the funtion.

 

My guess is that there is a problem with the line 7 instruction:

reg_val = Xil_In32(DMA9643_1_BASEADDR + AXI_DMAC_REG_IRQ_PENDING);

 

I think that I can't call "checkTransfert" two times, without doing something special with the interruption process. It would be great if you could help me on that as weel

 

Thanks in advance for your help

 

Clément

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