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D4 bit of 0x137 register in AD 9361

Question asked by Vibha on Apr 14, 2016
Latest reply on Apr 20, 2016 by Vibha

It is said that D4 bit of 0x137 register must  be "0" (Pg no 45 of UG-672 AD9364 Register Map Reference Manual) ,

0x137 register is used for Gain Table Clock and write gain table index, which depends on destination like on destination of rx antenna 1 (rx1) or destination of rx antenna 2 (rx2) or destination of rx antenna 1 and 2 (rx1 and rx2.)

 

ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG, START_GAIN_TABLE_CLOCK |RECEIVER_SELECT(dest)); /* Start Gain Table Clock */

 

ad9361_spi_write(spi, REG_GAIN_TABLE_CONFIG,START_GAIN_TABLE_CLOCK |WRITE_GAIN_TABLE |RECEIVER_SELECT(dest)); /* Gain Table Index */

In our case we have destination as rx1, if we set the same like dest = 3 and set START_GAIN_TABLE_CLOCK  then the value of the register will be 26 (decimal) and it violates D4 bit condition  of 0x137 register, Similarly if we set WRITE_GAIN_TABLE with dest as 3 then the value of the register will be 30(decimal), and it also violates D4 bit condition of 0x137 register .

So I think we should change dest as 5  then the then the value of the register will be 10 (decimal) and 14 (decimal) for START_GAIN_TABLE_CLOCK and WRITE_GAIN_TABLE.so that it don't violates D4 bit condition.

 

Can anyone please confirm this?

 

enum fir_dest {

                FIR_TX1 = 0x01,

                FIR_TX2 = 0x02,

                FIR_TX1_TX2 = 0x03,

                FIR_RX1 = 0x81,

                FIR_RX2 = 0x82,

                FIR_RX1_RX2 = 0x83,

                FIR_IS_RX = 0x80,

};

enum fir_dest dest;

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