AnsweredAssumed Answered

rx and tx path clock frequency set

Question asked by angleIsDancing on Apr 13, 2016
Latest reply on Apr 14, 2016 by DragosB

Hi, all.

In the No-Os project,to get a 30.72 MPSP rate,there are code below:

 

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/* Rate & BW Control */

  {983040000, 245760000, 122880000, 61440000, 30720000, 30720000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

  {983040000, 122880000, 122880000, 61440000, 30720000, 30720000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

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my questions are:

1.To get a 30.72 MPSP rate, why should set rx&tx path clock frequencies to the values shown in the code?

2.To set ADC_CLK ,we can set register BBPLL Divider[2:0], but to get other frequencies, which registers can we set?

thanks.

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