Is there a location for the AD9656 HDL that I would be able to view? Has anyone at ADI done any Vivado development for the AD9656 ADC and has a shareable project?
The AD9656 capture FPGA source code has been emailed to you.
I hope your project goes well.
Thanks for your interest in AD9656. By "AD9656 HDL" do you mean FPGA source code to capture AD9656 outputs?
Exactly - looking for the IP block to allow for AD9656 interfacing. All of us users on the forum and elsewhere have had a lot of success with the ADI-supplied IP blocks in the Git tree, such as for the 9250 and especially the 9361, support for that has been phenomenal... But the 9656 part support seems strange - it's recommended for new designs, has double the channel count of its competitors, but the reference for it is a Virtex-6 carrier card, and the source code for the HDL isn't obviously available? Weird...
I can provide the FPGA source code, but we cannot include any IP from Xilinx. I'll send you an email with more information.
Excellent! Will be looking out for that. Thanks for your help.
Could you email me the capture FPGA source code as well? I'm working a project on ZC706 to capture output from AD9656 through FMC and down convert by ddc.
It is sent.
Can you please send me that source code as well? I have an access to both ZC706 and KC705 so each version fits me.
AD9656 sample FPGA capture code (written for Xilinx Virtex6) has been sent to you.
Thank you for considering the AD9656.
Can you send this "AD9656 sample FPGA capture code" for me?
It has been sent.
Is there any chance I could get the code for the AD9656? We are doing a development with a Trenz TE0808 Zynq Ultrascale+ board. The eventual product will use an AD9671 and Xilinx ZU4CG. I wanted to use the AD9671 for the evaluation. However as the AD9671 evaluation board is no longer available so we decided to go with the AD9656 to evaluate the JESD204 serial link only to find no HDL in the github for it.
May I have "AD9656 sample FPGA capture code (written for Xilinx Virtex6)".
My customer and me in trouble for using AD9656 interface.
The code has been sent to you.
I need your help for my recent project with AD9656 with ZC706.
I have read above.
May I have AD9656 capture code for ZC706.
Thans in advance.
Thank you for using the AD9656. Unfortunately I do not have code written for ZC706. The standard capture board for the AD9656 uses a Xilinx Virtex6 FPGA. We have sample capture code written for this FPGA, if that would help you.
Thanks for your kind.
I appreciate code for virtex.
2017. 8. 22. 오전 10:04에 "DougI" <email@example.com>님이
EngineerZone <https://ez.analog.com/?et=watches.email.thread>Re: AD9656 HDL? reply from DougI<https://ez.analog.com/people/DougI?et=watches.email.thread> in *High-SpeedADCs* - View the full discussion<https://ez.analog.com/message/314421?commentID=314421&et=watches.email.thread#comment-314421>
Re: AD9656 HDL?
reply from DougI
<https://ez.analog.com/people/DougI?et=watches.email.thread> in *High-Speed
ADCs* - View the full discussion
The sample code has been sent.
Please take care.
Could you send me the hdl code for ad9656? I am using the virtex 6 to interface with ad9656.
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