I just updated to the latest No-OS driver and noticed the following comment in ad9361.c:
|/* The FIR filter once enabled causes the interface timing to change.|
|* It's typically not a problem if the timing margin is big enough.|
|* However at 61.44 MSPS it causes problems on some systems.|
|* So we always run the digital tune in case the filter is enabled.|
|* If it is disabled we restore the values from the initial calibration.|
I haven't been using the FIR filter, but will need to. I've designed the FPGA to meet the published timing specs for the 2 Rx/2 Tx mode. Are the timing numbers different than the datasheet values once the filter is enabled?