In a design based on 21489, I try to use sport0 A channel as 64-channel TDM sender and sport1 A channel as 64-channel TDM receiver. SPORT0 receive audio data of TDM from FPGA. The sampling frequency of I2S is 48kHz, and CLKIN on this ez-board is 25MHz. I would like to ask some questions .
1. I want to confirm whether each SPORT(A or B) supports up to 128 channels or not ? Or,both the serial data A and B channels of each sport supports up to 128 channels ?
2. Is the only way to generate Bit Clock and FS by using PCG ? PCG input clock selection is from oscillator(12.288MHz) on my ez-board.
3. I use packed I2S mode and 64-channel TDM, then how to calculate the value of Bit Clock and FS ? Maybe the value of Bit Clock is more than 100MHz,so I would like to know the feasibility of TDM data transmission between FPGA and DSP in
such a high Bit Clock .
I am also looking for some relevant example code.
So any one can give me some suggestions on these problems?