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PLL simulation

Question asked by Dingshang on Apr 8, 2016
Latest reply on Apr 20, 2016 by dyoung1

I want to multiply a 5MHz clock to 500MHz (or 10M to 1GHz ), in this process, the phase noise that the frequency multiplier brings  should be the least. And I find the integrated PLL chip HMC830 is a good choice.meanwhile  the combination of these chips hmc984(the intergrated digital frequency and phase detector),hmc983(the integrated divider),hmc510(the integrated VCO) also can achieve the desired effect. so compare these two ways ,which one is the best?

So how to simulate this system that combination of these three chips to get the curve of phase noise ?

thank you.