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ADF4355-2 close-in frequency independent spur problem

Question asked by dmarcosgon on Apr 8, 2016
Latest reply on Apr 18, 2016 by rbrennan

Hello,

 

We're having an issue with a design that implements an ADF4355-2. The problem? well, this is how the output looks like while set to an integer multiple of the reference frequency:

 

Screen_0032.png

The reference frequency is 122,88 MHz, derived from a TI dual loop PLL (LMK04821) and the ADF was set to 1966,08 MHz (16*122,88) so we shouldn't have integer boundary problems. We basically use a very stable 24,576 MHz reference to stabilize a very low phase noise VCXO through a first PLL, and then that stable 122,88 MHz signal drives a secondary frequency synthesizer which then gets divided to get all the clock references, including ADF4355's. Due to a still unknown issue (this is a prototype  and we're starting to debug it) the first PLL of the LMK not always locks so it disables and the secondary PLL takes the reference directly from the VCXO which produces an extremely clean signal (no spurs there) but with some frequency error and slow drift, as can be seen in the capture (about 153 Hz error). When it does lock the frequency is spot-on but today I couldn't get it to lock, however the spur problem happens anyway.

 

These close-in spurs happen no matter what frequency we set the ADF to. They reduce their levels when output frequency is lower.

 

The ADF4355-2 is driven by the official  ADI Linux driver. Here's the loop filter:

Loop.png

The output you see in the captures was taken from RFOUTB-. RFOUTB- and RFOUTB+ are both terminated the same way with a 50 ohm load. RFOUTB+ goes straight to the load while RFOUTB- has a series Murata SWF connector (switch-disconnect) and we tap from there.

 

 

Here's the DTS instantiation:

 

adf4355-main@0 {

                    compatible = "adi,adf4355-2";

                    reg = <0>;

                    spi-max-frequency = <1000000>;

                    clocks = <0x8>;

                    clock-names = "clkin";

                    clock-output-names = "mainol";

                    adi,charge-pump-current = <900>;

                    adi,muxout-select = <6>;

                    adi,output-a-power = <3>;

                    adi,output-b-power = <3>;

                    adi,output-b-enable;

                    adi,output-a-enable;

                    adi,charge-pump-negative-bleed-enable;

                    adi,reference-differential-input-enable;

                    adi,power-up-frequency = /bits/ 64 <122880000>;

                };

clock 0x08 is set to 122,88 MHz. Clock reference is differential LVPECL.

Any clue about what might be happening?

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