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Incorrect video at output ADV7511 10 bit upconverted SD 4:4:4

Question asked by MichaelBroesamle on Apr 7, 2016
Latest reply on May 2, 2016 by GuenterL

Register 4Ch dupper nibble isplays the wrong pixel phase 2 instead of 0. The input is 4.2:2 SD-SDI data. 625/50i 10 bit. Intended output is upconverted 4:4:4 10 bit. The 8 and 12 bit modes deliver a correct output image..In 3x10 bit output mode (corrupted image) the Quantum HDMI Test instrument displays an HSYNC width error: width=124 respective 128 instead of 126 in the nondisturbed case. Using the input mode YCbCr 4:2:2 2x clock embedded sync delivers a corrupted image  Using YCbCr 4:2:2 2x clock seperate sync has 50% Chance of correct or incorrect output images. Is there a way to influence the pixel packing phase? There must be!?!

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