By default (at power on), what is the active edge for the ADV7612 output pixel clock - LLC?
Figure 4 in the data sheet shows the pixel clock timing. Pixel data is valid on the rising edge of LLC
From the figure 4 of the datasheet, I understand that the ADV7612 by default, gives out pixel data at the negative edge of the clock. The interfaced device should capture the data at the next positive edge of the clock.
Please confirm if this is correct.
Yes, the output data changes on the falling edge and you need to latch it on the following rising edge.
Please find below the CRO snapshots showing LLC (first waveform) and P0 (second waveform) for 1080p60 video (148.5 MHz clock frequency).
From these waveforms, it looks like ADV7612 by default gives out pixel data at positive edge of the clock. Please note that we have not changed the LLC polarity , INV_LLC_POL = 0.
Could you please re-check and let us know the default active output edge of LLC?
This information is critically needed for us as we need to decide on the clock edge for capturing ADV7612 pixel data at the interface device.
Any update on this query?
Sorry I was not able to reply sooner. I have alot of questions I'm am trying to deal with at the moment.
So the datasheet is correct that it states that inside the ADV7612 data changeover occurs during the negative edge of the LLC. So in an ideal world you would sample the data on the rising edge of the LLC.
However in the real world the LLC and data may become misaligned due to PCB trace length, non-matching and other PCB imperfections. This issue is particularly apparent at high frequency (e.g. 148.5 MHz). This issue will occur on every high speed TTL interface (i.e. this issue is not specific to the ADV7612).
In order to get around this issue, a number of controls are available in the ADV7612 to skew the LLC versus the output data to achieve suitable setup and hold times for any back end device.
LLC_DLL_Phase adds phase offsets to the LLC clock, and INV_LLC_POL inverts the polarity of the LLC clock. See LLC controls section of the ADV7612 hardware manual for more information.
You need to modify the LLC in order to compensate for the effect of your PCB traces etc. If you are using an oscilloscope to measure the LLC data line offset, please measure this as close to the TTL receiver as possible.
Senior Applications Engineer,
Analog Devices INC.
Thanks for the response.
The difference in PCB trace length between LLC & P0 is around 26 mils. So the skew between data & clock is approximately 4.4ps (considering the delay of 170ps for trace length of 1000 mils). This skew is negligible and will surely not contribute to the large misalignment between clock and data.
As per the CRO waveforms, the clock to data valid delay for negative edge is 5.1 ns, which is very large when compared to datasheet value (negative clock edge to start of valid data = 0ns typ, 0.3ns max).
Please note that we have measured these waveform as close as possible to the receiver.
Also note that we have enabled the DLL block on the output clock. Will it cause any change in the active clock edge?
Yes the DLL block affects the phase of the LLC output clock. You need to adjust the DLL in order to achieve the optimal data sampling scheme for your system. Ensure that the setup and hold specifications as defined in your receiver datasheet are met.
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