We are currently using the AD9951 DDS for agile LO synthesis but encounter a problem regarding the leakage of the SYNC_CLK onto the DAC output. We are clocking the DDS at 384 MHz, +3 dBm sinusoid, thus the SYNC_CLK is at 96 MHz (REFCLK/4). Our LO range is from 70-100 MHz so this spur falls in-band and cannot be passively filtered at the DAC output. I read in the datasheet that the SYNC_CLK output can be disabled but the internal circuitry still runs so it doesn’t help. Are there any other ways to eliminate or minimize this spur?