AnsweredAssumed Answered

Pogramming the AD9517-4

Question asked by Orlando on Apr 6, 2016
Latest reply on Apr 6, 2016 by neilw

My design is based on the reference design: UG-328-DesignSupport from Analog Devices, Basically it consist of a AD9517-4, and the AD9253. In my design I program the different blocks from a Zynq FPGA.

I am trying to program the AD9517-4 with no completelly success. I can play arround with the LD, REFMON, and STATUS pins, mor¡nitoring different internal signals, so this proves my SPI bus is working OK. However PLL (AD9517-4) does not look.

Although I know the PLL (AD9517-4) is not locked I play around, doing:

My reference signal is 10MHz that is connected to REF1 (pin 48) and to CLK  (pin 11).

If I set CLK as source:


then I can se the CLK signal internaly divided (VCO DIV = 3 and DIVIDER0 =7) in the output 0 (pins 41 and 42) a signal of 476,2kHz (as it is supposed to be)

if I select VCO (1500MHz) as source (VCO DIV = 3 and DIVIDER0 =7)


i get no signal at all, just zero volts. Even though the PLL is not locked I should se a frequency division of the not locked PLL, shouldn´t I?


The VCO cal is another mistery this is my programming file


































































and then to cal VCO I do







Please help me!!!!