There appear to be sensitive nodes/pins on the ADRF6850 evaluation board, at least according to the PCB layout in the ADRF6850 rev 0 data sheet. There's even a note in the schematic: "Layout Note 4: Cut outs to be placed under caps on pins 45 & 48." However, those are ground pins with no connected capacitors located nearby. The PCB layers show some effort was made to keep copper out of the region near this part of the IC. But I'm unclear why this is necessary -- I see no reason given in the data sheet, outside of the note in the schematic. I'm curious to know if this note is correct, and what are the reason/requirements for the cut out region.