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AD9781 input port timing

Question asked by ilovephysics on Jul 9, 2011
Latest reply on Aug 22, 2011 by Tguy

I am working on a project involving AD9781. I have a couple questions.


1. I have a 500 MHz clock. This clock is sent to both the DAC and my FPGA which steams data to the DAC. In this design, since the FPGA already has a copy of the 500MHz clock directly from the master clock source, is using DCO from the DAC still necessary? I will still be able to optimize the input port timing by following the procedure described in page 25 of the data sheet, without DCO's involvement, correct?



2. Is the low jitter requirement on DCI (data clock input) as stringent as it is on CLKP/CLKN (DAC sampling clock input)? Assume I can get a low jitter DAC clock with at most 10 ps jitter, would 100-200 ps jitter on DCI be a significant problem? (the DCI comes from the FPGA whose output has more jitter than the 500 MHz clock from the master clock source.)



3. Since the input data is sampled on both the rising and falling edges of clock input, does this mean that the LVDS input data can go up to 1000 MSPS and thus after retiming and demux, gives 500 MSPS to I DAC and Q DAC respectively?  


Thank you very much for your help!