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AD5065 SPI Interfacing Problem

Question asked by davidcw on Apr 3, 2016
Latest reply on Apr 7, 2016 by davidcw

I'm trying to use a Teensy 3.2 microcontroller to control a AD5065 DAC, but am running into SPI timing issues. In particular, the  datasheet for the AD5065 states:
"The SYNC line must be brought high within 30ns of the 32nd falling edge of SCLK."
This timing requirement seems incredibly tight, and I can't seem to get my microcontroller, even with hardware SPI and a 96Mhz CPU clock to meet it. The best I can do is ~60ns. For the Teensy, a 96Mhz CPU clock allows for a maximum 24Mhz SPI clock, which is equivalent to ~41 ns SPI clock period.

Is there someway to avoid this strict "30ns" timing requirement, so 60ns would be okay?

i.e. Is there another operating mode of the DAC?