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Clock distribution at 5V

Question asked by Benure on Apr 2, 2016
Latest reply on Apr 12, 2016 by JLKeip


I'm making a ADC card with 6 AD7760 on it. Those chips takes a clock of 40Mhz at 5V. The input impedance is 7.2pF. So it's about 10mA per device.

 

My issue is that not many clock chips are in the 5V. I would like to keep the skew and jitter a small as possible. The rest of the component are high performance, so I don't want to add noise because of poor choice in the clock distribution.

 

In the referance design, the board has a AND gate for buffer/translator (NC7S08). But I can't really find a similar buffer that can feed 60mA at 5V.

 

The other option would be to feed each clock seperatly, but I don't know enough about device to know if that would bring skew noise and also add in the PS because of the skew in the clocks.

 

I don't have that much experience in the clocking, especially in the 5V. So if anyone could give me some insight as to how I can minimise the noise as much as possible, I would appreciate greatly.

 

Ben

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