We are making a Audio PCB using the ADAU1452, this PCB has analog input and digital input, analog input is from an adc connected to input bank2, for the digital input we use the S/PDIF receiver. We use ASRC0 to lock on the S/PDIF signal, however every time we upload the program into the dsp (using Sigmastudio) the clock divider for clock generator 1 changes from 6 to 2, causing the pcm clocks to be 3 times to fast. Disabling the ASRC sets the divider back to 6.
At this point we have no idea why this happens... Is this expected behavior? or is the dsp chip broken?