AnsweredAssumed Answered

Unable to write into SPORT transmit register TX

Question asked by Raghupathi_Kokkarakonda on Mar 30, 2016
Latest reply on May 3, 2016 by Jithul_Janardhanan

Hi,

 

I have the following code, My intention is to check that the SPORT1_TX register is getting update with the value is assigned to it and data has to be transmitted and received in loop back mechanism. I am using BF537 EZ KIT.

IDE : CrossCore studio

/*****************************************************************************

   Syncronous_Serial_Communication.c

*****************************************************************************/

 

 

/********************************************************/

 

 

#include<cdefbf537.h>

#include<ccblkfn.h>

#include<sysreg.h>

#include <sys\exception.h>

 

 

/********************************************************/

 

 

#define TFS_DIV 15 // Refer HRM for calculation of TFSDIV register

#define TCLK_DIV 10 // Refer HRM for calculation of TCLKDIV register

 

 

#define RFS_DIV 15 // Refer HRM for calculation of RFSDIV register

#define RCLK_DIV 10 // Refer HRM for calculation of RCLKDIV register

 

 

 

 

void Init_PLL(void);

void Init_data(void);

void Init_INTRs(void);

void Init_Tx_DMA(void);

void Init_Rx_DMA(void);

void Sport_Init(void);

 

 

EX_INTERRUPT_HANDLER(SPORT1_DMA_TX_ISR);

EX_INTERRUPT_HANDLER(SPORT1_DMA_RX_ISR);

EX_INTERRUPT_HANDLER(SPORT1_core_TX_ISR);

EX_INTERRUPT_HANDLER(SPORT1_core_RX_ISR);

 

 

#define BUFF_SIZE 100 // No. of data to transfer

unsigned short Tx_BUFF[BUFF_SIZE];

unsigned short Rx_BUFF[BUFF_SIZE];

volatile int Tx_count, Rx_count;

/**********************************************************/

 

 

void main()

{

  Init_PLL();

  Init_data();

  //Init_INTRs();

 

 

  #ifdef DMA_mode_operation

  Init_Tx_DMA();

  Init_Rx_DMA();

  #endif

 

 

  Sport_Init();

 

 

  *pSPORT1_TX = 0x1111;

 

 

  *pSPORT1_RCR1 |= RSPEN;

  *pSPORT1_TCR1 |= TSPEN;

 

 

  //while(~(*pSPORT1_STAT & 0x1)){};

 

 

  Rx_BUFF[Rx_count++] = *pSPORT1_RX;

 

 

}

/************************************************************/

 

 

void Init_PLL(void)

{

  unsigned long temp = *pSIC_IMASK;

  *pPLL_CTL = 0x2000;

  *pPLL_DIV = 0x0005;

  *pVR_CTL = 0x40DB;

  *pSIC_IMASK = 0x0;

  *pSIC_IWR |= 0x1;

  *pSIC_IMASK = temp;

}

 

 

/************************************************************/

 

 

void Init_data(void)

{

  long i, j;

  for (i = 0; i < BUFF_SIZE; i++, j += 0x1111)

  {

  Tx_BUFF[i] = j;

  }

}

/*************************************************************/

 

 

void Init_INTRs(void)

{

  #ifdef DMA_mode_operation

  register_handler(ik_ivg9, SPORT1_DMA_RX_ISR);

  register_handler(ik_ivg9, SPORT1_DMA_TX_ISR);

  #else

  register_handler(ik_ivg9, SPORT1_core_RX_ISR);

  register_handler(ik_ivg9, SPORT1_core_TX_ISR);

  #endif

  *pSIC_IAR0 |= 0x20000000;

  *pSIC_IAR1 |= 0x00000002;

  *pSIC_IMASK |= 0x00000180;

}

 

 

/****************************************************************/

 

 

void Init_Tx_DMA(void)

{

  *pDMA6_START_ADDR = Tx_BUFF;

  *pDMA6_X_COUNT = BUFF_SIZE;

  *pDMA6_X_MODIFY = 0x02;

  *pDMA6_Y_COUNT = 0x00;

  *pDMA6_Y_MODIFY = 0x00;

  *pDMA6_CONFIG = WDSIZE_16 | DI_EN | DMAEN;

}

 

 

/****************************************************************/

 

 

void Init_Rx_DMA(void)

{

  *pDMA5_START_ADDR = Rx_BUFF;

  *pDMA5_X_COUNT = BUFF_SIZE;

  *pDMA5_X_MODIFY = 0x02;

  *pDMA5_Y_COUNT = 0x00;

  *pDMA5_Y_MODIFY = 0x00;

  *pDMA5_CONFIG = WDSIZE_16 | DI_EN | WNR | DMAEN;

 

 

}

 

 

/****************************************************************/

 

 

EX_INTERRUPT_HANDLER(SPORT1_core_TX_ISR)

{

  *pSPORT1_TX = Tx_BUFF[Tx_count++];

  // Put the data in transmit_buf to transmit register

 

 

  if(Tx_count == BUFF_SIZE)

  {

  *pSIC_IMASK &= 0xFFFFFEFF;

  }

}

 

 

/****************************************************************/

 

 

EX_INTERRUPT_HANDLER(SPORT1_core_RX_ISR)

{

  Rx_BUFF[Rx_count++] = *pSPORT1_RX ;

 

 

  if(Rx_count == BUFF_SIZE)

  {

  *pSIC_IMASK &= 0xFFFFFF7F;

  }

}

 

 

/****************************************************************/

 

 

EX_INTERRUPT_HANDLER(SPORT1_DMA_TX_ISR)

{

  while(!(*pDMA6_IRQ_STATUS & DMA_DONE));

  *pDMA6_IRQ_STATUS = DMA_DONE ;

}

 

 

/****************************************************************/

 

 

EX_INTERRUPT_HANDLER(SPORT1_DMA_RX_ISR)

{

  while(!(*pDMA5_IRQ_STATUS & DMA_DONE));

  *pDMA5_IRQ_STATUS = DMA_DONE ;

  *pSPORT1_RCR1 &= ~RSPEN;

}

 

 

/****************************************************************/

void Sport_Init(void)

{

 

 

 

 

  /*SPORTx Transmit Configuration 1 Register (SPORTx_TCR1)*/

  *pSPORT1_TCR1 |= ITCLK; /*Internal Transmit Clock Select */

  *pSPORT1_TCR1 |= DTYPE_NORM; /* Data Formatting Type - Normal Operation */

  *pSPORT1_TCR1 |= TLSBIT; /* Transmit Bit Order - LSB */

  *pSPORT1_TCR1 |= ITFS; /* Internal Transmit Frame Sync Select */

  *pSPORT1_TCR1 |= TFSR; /* Transmit Frame Sync Required Select */

  *pSPORT1_TCR1 |= DITFS; // Matt Suggested

 

 

  /*SPORTx Transmit Configuration 2 Register (SPORTx_TCR2)*/

  *pSPORT1_TCR2 |= SLEN(15); /* SPORT TX Word Length (2 - 31) */

  //*pSPORT1_TCR2 |= TSFSE; /* Transmit Stereo Frame Sync Enable */

  //*pSPORT1_TCR2 |= TXSE; /* TX Secondary Enable */

  //*pSPORT1_TCR2 |= TRFST; /* Left/Right Order (1 = Right Channel 1st) */

 

 

  /*SPORTx Receive Configuration 1 Register (SPORTx_RCR1)*/

  *pSPORT1_RCR1 |= IRCLK; /* Internal Receive Clock Select */

  *pSPORT1_RCR1 |= DTYPE_NORM; /* Data Format Normal */

  *pSPORT1_RCR1 |= RLSBIT; /* Receive Bit Order */

  *pSPORT1_RCR1 |= RFSR; /* Internal Receive Frame Sync Select */

  *pSPORT1_RCR1 |= RCKFE; /* Clock Falling Edge Select */

 

 

  /*SPORTx Receive Configuration 2 Register (SPORTx_RCR2)*/

  *pSPORT1_RCR2 |= SLEN(15); /* SPORT RX Word Length (2 - 31) */

  //*pSPORT1_RCR2 |= RSFSE; /* RX Stereo Frame Sync Enable */

  //*pSPORT1_RCR2 |= RXSE; /* RX Secondary Enable */

  //*pSPORT1_RCR2 |= RRFST; /* Right-First Data Order */

 

 

  /*Note RFSDIV or TFSDIV must still be greater than or equal to SLEN.*/

  /*TSCLKx frequency = (SCLK frequency)/(2 x (SPORTx_TCLKDIV + 1))

  * RSCLKx frequency = (SCLK frequency)/(2 x (SPORTx_RCLKDIV + 1))*/

  *pSPORT1_TCLKDIV = TCLK_DIV;

  *pSPORT1_TFSDIV = TFS_DIV;

 

 

  *pSPORT1_RCLKDIV = RCLK_DIV;

  *pSPORT1_RFSDIV = RFS_DIV;

 

 

  *pPORT_MUX = PGTE|PGRE|PGSE;

  *pPORTG_FER = 0xFF00;

 

 

 

 

// *pSPORT1_TCR1 = (TFSR  | TLSBIT | ITFS | ITCLK);

// *pSPORT1_TCR2 |= SLEN(15);

//

// *pSPORT1_RCR1 = RFSR  | RLSBIT;

// *pSPORT1_RCR2 |= SLEN(15);

//

// *pSPORT1_TCLKDIV = TCLK_DIV;

// *pSPORT1_TFSDIV = TFS_DIV;

//

// *pSPORT1_RCLKDIV = RCLK_DIV;

// *pSPORT1_RFSDIV = RFS_DIV;

//

// *pPORT_MUX = PGTE|PGRE|PGSE;

// *pPORTG_FER = 0xFF00;

 

 

}

 

I connected , SPORT pin P10 -> pin12, and pin8 to pin 14.

 

Need help ASAP.

Outcomes