I have an I2S master application, using 32 bit Clk Cycles/Frame (16 bit / channel). I can't figure out if the ADAU1761 is able to use 32 bits Clk Cycles/frame. As far as I can see, the minimum is 48 bits.
Unfortunately, the serial port implementation on this device is somewhat limited.
Is there a way to change the source to be true I2S where there are 32 BCLKs per channel? (64 per frame)
Perhaps I can help you select a different SigmaDSP processor if you tell me your needs?
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