I am trying to implement a predistortion loop with the adau1701. This means that a signal will be send out to the DA converter of the ADAU1701 and goes into a DUT ( which is a non linear process ). The resulting signal is sampled back in via the AD converter of the ADAU1701.
I would assume there is a fixed (phase )delay between the DA and AD ports which is equivalent to the sample blocksize.
In other words, if i output a 1khz sine to the DA and sample it back in via the AD, i would suspect a delay.
This delay should be frequency independent., however after doing some tests i found out that this delay is frequency dependent. This is quite odd.
The test is as following:
Create a 500Hz sine block output it to DA0, sample this signal back in with a cable via AD0 and output the AD0 signal to DA1. Connect the oscilloscope to DA0 and DA1 ( 2 channel scope ). Look at the phase shift. Now change the frequency to 2000 Hz and observe the phase shift again. This is not a constant value as i would assume.
Is this an architectural issue?