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What is minimum safe delay time required for filling the command FIFO?

Question asked by Carlo.Astel on Mar 29, 2016
Latest reply on Apr 5, 2016 by emoloney

I had faced some unknown problems when I wrote my sequence and I found the solution in this thread:

 

https://ez.analog.com/thread/81664

Another source of this error is a little trickier to find if you don't know about it! The command FIFO (which the core fills with commands and the sequencer empties) is 8 commands deep. The core will typically use the DMA to fill the FIFO. The sequencer removes these commands from the FIFO as they are needed. As the FIFO empties, an interrupt will trigger the DMA to fill it again. The sequencer will execute each MMR writes in a single clock cycle (62.5ns). If the FIFO is filled with 8 MMR writes, then the FIFO will be emptied in 8 clock cycles. In this scenario, the DMA is not fast enough to fill the FIFO again before the sequencer attempts to take another command, which triggers an underflow error. The simplest workaround here is to ensure that there are never any more than 7 MMR writes in succession and to break up any more than that using a short wait command. An example of this can be seen in the seq_afe_dcmeas sequence in afe_sequences.h.

 

My question is: what it the minimum safe delay to put between each 7 words to avoid this problem?

The examples put 100us but, although I have not measured a speed, it seems a bit exagerated to me.

 

Thank you very much.

 

Sincerely.

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