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Synchronisation primitives across cores

Question asked by Vrnc on Mar 28, 2016
Latest reply on Apr 5, 2016 by stevek

In the SC58x devices, ARM core plus Sharc cores...

In the ARM core, LDREX and STREX are used to provide exclusive access for semaphore like constructs.
In the Sharc, the delayed branching provides atomic operation for the same...

  jump (pc, 3) (db):

  instruction 1;

  instruction 2;

 

Assuming the cores have the appropriate access rights to the same area of memory, do these primitives operated as expected between cores?

 

If not, what primitives do?

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