I'm working with a custom design based on the reference design FMCMOTCON2(hdl_2015_r1.zip) by using XILINX System Generator.
There are some brief descriptions for my custom design below:
1. The design is aimed to realize the FOC algorithm.
2. With the IP n_soll I want to use the four lower GPIO Switches(SW0-SW3) to generate a reference rotor speed named "n_soll" ranging from 0 rpm to 6000 rpm. In addition, SW7 decides the rotation direction. SW7=OFF, counterclockweise; SW7=ON, clockweise.
3. With the help of the input signal position_m1_i[2:0] of the ADI IP speed_detector_m1, the electrical angle "theta" and the rotor speed will be detected by the custom IP encoder. The output signal speedm1[11:0] of this IP stands for the rotor speed, that is directly converted from the signal position_m1_i[2:0]. However, the output signal speedfir[1:0] is speed data stream, that can also be the rotor speed after being filtered by the IP fir.
5. The IP n_ist_1aus2 can choose one of the two speed input signals by toggling SW6. This means that SW6=0, rotor speed without being filtered as the output signal; SW6=1, filtered rotor speed.
6. The IP Core i_mess converts phase currents ia and ib from the ADI IP current_monitor_m1 into currents id und iq by using the clark und park transformations.
7. In the IP regler the speed controller and current controller are designed. This IP generates two reference voltages in d/q-coordinate named "ud_soll" and "uq_soll".
8. With the IP timesection and svpwm we can calculate the reference space vector and generate the drive signals for the power stage. The output ports in the IP svpwm pwm_x (x=a, b or c) are respectively connected with the input ports pwm_x_i (x=a, b orc) of the ADI IP controller_m1.
After integrating these IPs into the reference design and making connections, I made synthesis and implementation successfully. However, with the Zedboard programmed, the motor in the test bench didn't spin, though I toggled the switches I had defined before. I have no idea about why this custom design doesn't function as desired.
In the attachment you can find the block design in PDF-Format, in which all of the eight custom IPs are on the left of the block design.