I have a question regarding AD7606 configuration. I built a circuit where I use this ADC converter for audio applications. I attach you a picture of the schematic and of the time diagrams I get through the logic analyzer.
SCLK = 12.5 MHz. 50 % Duty cycle
V overdrive = 3.3 V
Vdd = 5 V
Time between busy falling edge and CS_n falling edge equal to 60 ns.
Time between CS_n falling edge and SCLK falling edge equal to 30 ns.
Serial reading using DAout.
No digital filter used.
However, as you can see in the logic analyzer time diagram I am not getting any signal in the DAout channel (labeled as DB7). Good new is that I am receiving a correct BUSY signal.
I would like to ask you if you can realize what is missing in my design or schematic, or if the timing of my design is not correct.
Thanks for your attention and if you need further details or have any question about the design please contact me ( I hope you can correctly see the attached pictures). I really need some help because I am really stack at this point and I do not really see the solution. Thanks a lot!!