Today I've had a real long look at the datasheet, trying to figure out the lowest sawtooth frequency possible given a certain clock frequency CLK. This information is critical to see if I need two separate IC's or if I can do with a single AD9106.

From the four lines on page 27 (Rev. A), I assume that the sawtooth generator runs at CLK and you can divide the clock up to 64x by means of SAW_STEPx field, thus each sawtooth step would take 64/CLK seconds. To calculate the sawtooth frequency, I guess I would need to know the number of steps, i.e. the number of bits of the sawtooth waveform counter?

Let's say that CLK = 180MHz, the sawtooth generator has 12 bits (i.e. 4096 steps) and the SAW_STEP register is 63, the lowest sawtooth frequency would be (180MHz/63)/4096 = 697.5Hz, correct? Can anyone confirm the number of steps for a full sawtooth waveform?

I do realise that one can lower the frequency by choosing a lower CLK frequency, the question comes down to 'what is the biggest difference in frequency between the DDS sine wave and sawtooth waveform?'

Thanks in advance!

Tests with the AD9106 have shown that with a clock of 174.8MHz and SAW_STEP set to 32, the ramp frequency is ~333.8Hz. Another setting, SAW_STEP = 55 gives about 195Hz. This would indicate that the sawtooth generator has 2^14=16384 steps and not 4096. The DDS frequency calculations are consistent with the datasheet, so I assume that this rules out erroneous register settings on DAC hold etc. Luckily, this works in my benefit.

Larry, if you agree, could you mark my comment as 'correct', for others to use this information? If not, please advise where I could have made a mistake.

In short, the equation below gives consistently the correct sawtooth frequency in my setup:

f_{saw} = f_{dac}/(2^14 * SAW_STEP).