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AD7762 Mclk Fanout/Distribution, any wisdom on clk distribution will be welcomed

Question asked by Benure on Mar 22, 2016
Latest reply on Apr 2, 2016 by Benure

We are designing a card which will drive 6x AD7762. We would like them to be in synch as much as possible. I know that in order to obtain the maximum SNR we need to have this clock at 5V. I can't really find any Fanout/Clock distribution that work at that level. It is probably why the datasheet suggest a AND gate. I'm not too familiar with designing clock system with logic gate. I see a couple setup with PRO/CON and I don't have enough experience to know which would be recommended.

 

I could run a AND buffer on each AD7762.

     -I don't know if I will loose some of the synch because of small time responce variations between the AND Gates.

     -I don't know if having multiple AND gate with small timing differences will create additional noise in the system. (like having 6      different clock signal noise)

 

I could run 1 Buffer to feed them all on the same signal

     -I don't know the problem that parralleling multiple capacitance load will cause on the clock

     -I don't know if parralleling them will cause the clock edge to be more round with lower dv/dt

 

If anyone has any wisdom on clock signal, I would be really appreciate it. Our Mclk is 40Mhz @ 5V And is streaming continuously.

 

Ben

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