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AD9361 Multi Chip Synchronisation (MCS)

Question asked by Phn1234 on Mar 22, 2016
Latest reply on Apr 20, 2016 by Phn1234


We are using several AD9361 and would like to use the Multi Chip Sync (MCS) feature to sync the rx data clk outputs.

We are following the advised sequence, and indeed see the Rx Data Clks pulling into alignment with each other (with +/-1ns tolerance). However, we are finding that the alignment of the Rx Frame Sync and Rx data is shifting every time we run through the MCS sequence. We are using LVDS mode, so the four channels (IA/QA/IB/QB) are multiplexed onto a 6bit bus, with 12bit samples sent as 6 bit MS and LS. The frame sync is used to indicate the position of the data in the cycle, with the high portion of the frame sync marking the IA/QA data and the low period marking the IB/QB data :-

(so Iam = MS 6 bits of IA channel etc)



Before MCS (the high frame sync period marks the A channel data) :-

Rx FrameSync       1     /    1    /   1  /   1    /   0    /    0     /     0   /   0    Repeat

Rx Data                  Iam / Qam / Ial  / Qal  / Ibm / Qbm  /    Ibl  / Qbl


After MCS (the frame sync has now shifted with respect to the rx data) :-

Rx FrameSync       1     /     1    /   0  /   0    /   0    /    0     /     1   /   1    Repeat

Rx Data                  Iam / Qam / Ial / Qal / Ibm / Qbm / Ibl  / Qbl


This is causing the state machines in our FPGA which extract the data from the frame to get out of step.

Is this to be expected? Do we need to realign the data in our FPGA with some sort of training sequence?

Is anyone else seeing this behaviour? Is there something we need to do to get the data / frame back in alignment?