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Reassemble signal output jesd204B

Question asked by thotho on Mar 20, 2016
Latest reply on Mar 23, 2016 by JudyChui


I capture with chipscope the "sar_data_reg" signal in the "sample_reassembly" and I import the date in matlab to plot the wave.

I set the AD9625 with 0x0D register with the value 0X0F to generate a ramp in output.

The ADC configuration is: L=4, F=2, K=32.

I expect to find a ramp with 12 bits, but with chipscope I see a ramp with 8 bits as you can see in the attached.. This rampe is repeat 6 time, with 4 differents phase, so if I plot the resalts in matlab of all 6 sample some are coincident as in the attached where 2 sample are superimposed.

I axpect to find 4 samples for cycle of frame, one frame is composed of 2 octects, 12 bits of octecs must be the bits of rampe the other tile bits, am'I right?

But if the ramp signal has only 8 bits, and the 4 sample that I plot in matlab are exact ( they are the 4 samples for clock cycle) how can I merge their to obtain one ramp signal?

The signal "sar_data_reg" of "sample_reassemble" is it not already ordered?


Can you help me?