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Data Port Loop Test for AD9364

Question asked by leonid.k on Mar 19, 2016
Latest reply on Mar 21, 2016 by tlili

Hello people.

My role is a test engineer and I'm trying to build the test model for AD9364 to use with the ICT or Boundary Scan tests.

For now I'm working with a design where all digital interface signals of AD9364 connected  to FPGA ALTERA ARRIA V.

So by the Boundary Scan of the FPGA I succeed to work with SPI ineterface of AD9364 and read & write an internal registers.

But after I wrote the 0x3F5 register with 0x01 or 0x81 value and after that provide the TX bus with various values I don't see RX bus activity.

Sure I'm working with the FPGA erased before test and can supply low frequency TX CLK (to FB_CLK_P pin).

Can someone help me? What do I wrong?

The timing diagram of this process supplying will be a good help.

The schematic page attached.