Dear Analog Devices engineers and all,
We are looking at the phase noise performance of AD9144.
The datasheet specifies the single-tone phase noise over different output frequencies, when operating at 2GHz updating rate, as the following figure. By analysing the plot, we may conclude the FOM of the DAC starts to dominating the phase noise since the offset is larger than 400kHz.
However, it didn't give enough information about the clock source, apart from the on-chip PLL is disabled.
It seems the near-carrier phase noise is completely inherited from the 2GHz external clock source, instead of the flicker or other noise of the DAC itself.
Could Analog Devices engineers provide the missing piece of information about the clock source, or be even better by providing the residual phase noise of the chip?