I am working with AD9364 [+KC705] on a project.
First of all am using 2 AD9364.
Data flow is something like this :: Data is being sent from the fpga to one of the transceiver [AD0] which is connected to another transceiver [AD1] through a cable [txA to rxA] and the received data is sent back to fpga.
The data format of the input data[i/q] that is being given is a known q format sampled signal [q11] which is of 12 bit[1 signed + 11 fractional] plus 0 at its lower nibble.
My doubt : What would be the format of the received data samples after AD1 at the FPGA ??
Checking the code I found that the msb nibble represents data's sign and the other 12 bits refer to the input data. Is my understanding correct ??
If not, Please explain the way I have to consider the received data for analysis.
Here for my analysis, phase is of main concern. [as there will be definite data loss].
Thnaks in advance for your time and knowledge,