Has anybody got example code that maximizes the SPI baud rate in Master/Slave mode?
I am using the ADuC7023 and ADuC7122?
Ideally, I would like a half duplex and full duplex solution.
Master – AduC7023 but, could be ADuC7121, ADuC7122, ADuC7124, ADuC7126 – same code will maximize ADuC7060/61 SPI baud rate also.
Slave – AduC7023 but, could be ADuC7121, ADuC7122, ADuC7124, ADuC7126 – same code will maximize ADuC7060/61 SPI baud rate also.
If full duplex communication isn't required the SPI baud rate can be further increased because the master only needs to transmit and doesn't care what comes back. Similarly on the slave side you only need to poll the RX status bits and don't need to worry about loading SPITX
SPI was configured with a baud rate of 10MHz, and a transfer of 16 bytes took approximately 12uS. If a baud rate of 20 MHz was used the total transfer time didn't decrease because even though an individual byte was transferred quicker similar times were spent polling the status bits.
Also NOTE that when using 20MHz the master clock doesn't go fully to 0v for a low level. The low level is only at 760mV which is just about ok for communication between 2 x ADuC7023 chips because a logic LOW is 0.8v (max rating), but when using the 7023 with other parts it might not detect the clock.
On the master side, user code calls the assembly function, WriteSPI() when a transfer is required. A pointer to an array with bytes to be sent is passed into the function. The function checks if the TX FIFO is full and if not it copies a byte into SPITX. It repeats this until all the bytes have been transmitted.
On the slave side an FIQ is generated when 4 bytes have been received. The FIQ jumps to the assembly function, ReadSPI() which checks the status bits and reads SPIRX if there's a valid byte in the FIFO.
It is assumed that the SPI FIQ is the highest priority interrupt source on the part.
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