I have two questions regarding the clock design in AD-FMCOMMS1-EBZ design:
1) Is there any benefit to program the AD9523-1 Frequency output with 122.88MHz to both TX & RX LO (the lowest input is 10MHz),
Shall be able to use 30.72MHz. (in which fPFD=REFIN). Is it because better phase noise or other concern.
I have tried the ADIsimPLL tool, and running the simulation, but I got worse VCO phase noise using 122.88MHz reference input
(compared with 30.72MHz reference input. )
2) AD9548 was used here with 30.72MHz clock input from FPGA board.
I suppose the 30.72MHz clock could be directly connected to 9523-1 low-jitter cock distributor.
Is there any reason to use this ? (jitter cleanup to have clean clock output to ADC &DAC? )