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AD1939 PLL unlocked?

Question asked by wangzhichao on Mar 15, 2016
Latest reply on Mar 27, 2016 by wangzhichao

hi,

I used the DEMO of  "21489 AD1939 I2S C Sampled-Based Talkthru", but PLL lock indicator in PLL and Clock Control 1 Register is always UNLOCKED ?  get stuck in an infinite loop, marked in red .


at the same time, SPI is ok, it can write or read from AD1939's Registers.

 

#define USE_48_KHZ_SAMPLE_RATE

//#define USE_96_KHZ_SAMPLE_RATE

//#define USE_192_KHZ_SAMPLE_RATE

 

 

/* Setup the SPI parameters here in a buffer first */

unsigned char ConfigParam1939 [] = {

            (AD1939_ADDR), DACMUTE, 0x00,

            (AD1939_ADDR), CLKCTRL0, DIS_ADC_DAC | INPUT256 | PLL_IN_MCLK | MCLK_OUT_OFF | PLL_PWR_DWN,

            (AD1939_ADDR), CLKCTRL1, DAC_CLK_PLL | ADC_CLK_PLL | DIS_VREF,

#ifdef USE_48_KHZ_SAMPLE_RATE

            (AD1939_ADDR), DACCTRL0, DAC_FMT_I2S | DAC_BCLK_DLY_1 | DAC_SR_48K,

#endif

#ifdef USE_96_KHZ_SAMPLE_RATE

            (AD1939_ADDR), DACCTRL0, DAC_FMT_I2S | DAC_BCLK_DLY_1 | DAC_SR_96K,

#endif

#ifdef USE_192_KHZ_SAMPLE_RATE

            (AD1939_ADDR), DACCTRL0, DAC_FMT_I2S | DAC_BCLK_DLY_1 | DAC_SR_192K,

#endif

 

          (AD1939_ADDR), DACCTRL1,  DAC_BCLK_SLAVE| DAC_LRCLK_SLAVE  | DAC_CHANNELS_2 | DAC_LATCH_MID, //Ddebug

            (AD1939_ADDR), DACCTRL1,  DAC_BCLK_SLAVE| DAC_LRCLK_SLAVE  | DAC_CHANNELS_2 | DAC_LATCH_MID, //Ddebug

            (AD1939_ADDR), DACCTRL2, DAC_WIDTH_24,

#ifdef USE_48_KHZ_SAMPLE_RATE 

            (AD1939_ADDR), ADCCTRL0, ADC_SR_48K,

#endif

#ifdef USE_96_KHZ_SAMPLE_RATE 

            (AD1939_ADDR), ADCCTRL0, ADC_SR_96K,

#endif

#ifdef USE_192_KHZ_SAMPLE_RATE 

            (AD1939_ADDR), ADCCTRL0, ADC_SR_192K,

#endif

            (AD1939_ADDR), ADCCTRL1, ADC_LATCH_MID | ADC_FMT_I2S | ADC_BCLK_DLY_1 | ADC_WIDTH_24, 

 

          (AD1939_ADDR), ADCCTRL2, ADC_BCLK_SRC_INTERNAL | ADC_BCLK_MASTER | ADC_CHANNELS_2 | ADC_LRCLK_MASTER  | ADC_LRCLK_FMT_50_50|ADC_LRCLK_POL_NORM|ADC_BCLK_POL_NORM, // NDdebug

          (AD1939_ADDR), ADCCTRL2, ADC_BCLK_SRC_INTERNAL | ADC_BCLK_MASTER | ADC_CHANNELS_2 | ADC_LRCLK_MASTER  | ADC_LRCLK_FMT_50_50|ADC_LRCLK_POL_NORM|ADC_BCLK_POL_NORM, // NDdebug       

          (AD1939_ADDR), DACVOL_L1, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_R1, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_L2, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_R2, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_L3, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_R3, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_L4, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_R4, DACVOL_MAX,

            (AD1939_ADDR), CLKCTRL0, DIS_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT256 | PLL_PWR_UP,

            (AD1939_ADDR), CLKCTRL0, ENA_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT256 | PLL_PWR_UP,

            (AD1939_ADDR), DACMUTE, 0x00,

            } ;

void Init1939viaSPI()

{

    int configSize = sizeof(ConfigParam1939);

    int i,j=0 ;

    unsigned char tmpA[sizeof(ConfigParam1939) / 3];

 

    //Set up AD1939

    SetupSPI1939(AD1939_CS);

 

 

    //Write register settings

    for(i = 0; i < configSize-6; i+=3)

    {

        Configure1939Register(ConfigParam1939[i], ConfigParam1939[i+1], ConfigParam1939[i+2], AD1939_CS);

        Delay(272);

 

        //Read back register settings for debugging

        AD1938_Regs_Read[j++] = Get1939Register(ConfigParam1939[i+1], AD1939_CS);

        Delay(272);

    }

 

    // Make sure the PLL is locked before enabling the CODEC.

 

    LockTest = Get1939Register(0x1, AD1939_CS);

    while (!(LockTest & AD1938_PLL_LOCK))

    {

    LockTest = Get1939Register(CLKCTRL1, AD1939_CS);

    LockCount++;

    }

 

    for(i = configSize-6; i < configSize; i+=3)

    {

        Configure1939Register(ConfigParam1939[i], ConfigParam1939[i+1], ConfigParam1939[i+2], AD1939_CS);

        Delay(272);

 

        //Read back register settings for debugging

        AD1938_Regs_Read[j++] = Get1939Register(ConfigParam1939[i+1], AD1939_CS);

        Delay(272);

    }

    DisableSPI1939();

}

 

 

Others, I changed the Crystal Oscillator from 12.288MHz to 24MHz, the PLL is ok and locked.

Outcomes