Dear, When reference clock input circuitry is configured as an input buffer, the reference clock for Ad9959 can be either differential or single-ended configurations.
If I the complementary reference clock input (Pin 22) decoupled to AVDD or AGND via a 0.1 μF capacitor, what is the maximum allowed voltage at (Pin 23)?
If I use the configuration of figure 33 (datasheet rev B), what is maximum vaoltage for refclock source?
Does the second method has any advantages over the first one?
Thank you in advance