I am using a single 9957 with a DSP microprocessor interfaced via BFI mode. Turns out the application is sensitive to latency through the 9957, which, according to the data sheet (rev D) p45 is unknown and can vary. I thought that perhaps the latency could be controlled via the Multichip sync. If the chip was properly sync'ed then perhaps the latency would track the sync_out pulse. I had never tried syncing the chip and had no problems getting it to work in BFI mode.
I set the chip up to sync itself (connected sync out to sync in) and enabled sync. Now I find the chip can come up in either of two states randomly. In one state, after the sync, the BFI interface is trashed. The output of the chip is obviously based on corrupted input data. In the other mode, it works fine as before.
Why does syncing the chip break the BFI interface?
I do find that if the chip syncs with itself and comes up in the 'good' mode, the latency does track the sync_out pulse. However it is independent of the sync value written to the control register.
Also, I think the silicon was revised without properly revising all documents. There are bits and features in the AD9957 Dev kit Software that are not documented anywhere, such as 'Internal Sync Loop'. Any any way to get updated docs?