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ad9364 evm gets worse with time during every transmission

Question asked by NewsH on Mar 15, 2016
Latest reply on Mar 17, 2016 by tlili

Hi,

The ad9364 chip is used in a customized 802.11 RF board, which connecting to our FPGA via LVDS.

For convenience, the chip is working in FDD mode.

In our TX packet test, we find that the TX EVM get worse with time during each transmission.

IMG_20160315_121933_3.png

* The blue line is the real time EVM vs Symbol

* The orange line is the max EVM vs Symbol

 

Does anyone know what is likely causing this kind of trouble?

Thanks.

 

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Driver: Latest non-OS ad9361 driver

 

default_init_param parameters related to freq and bandwidth:

 

2440000000UL, //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz

{1280000000, 640000000, 320000000, 160000000, 80000000, 80000000},//uint32_t  rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

{1280000000, 640000000, 320000000, 160000000, 80000000, 80000000},//uint32_t  tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

40000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz

40000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz

 

After ad9361_main() is done, ad9361_set_tx_rf_bandwidth() is called to set the bandwidth to 20MHz, and ad9361_set_tx_lo_freq() is called to set the center freq to 2442MHz.

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