I need some help about AD9361's maximum sample data rate.
In "UG-570 Reference Manual (Rev. A)" Page 108 Table 50, when AD9361 is working in LVDS Mode, Dual Port Full Duplex and 1R1T Configuration, the Maximum Data Rate Combined I and Q Words (MSPS) is 61.44 MSPS.
However, UG-570 also said (Page 108):
The maximum DATA_CLK rate is increased to 245.76 MHz in LVDS mode.
then from the Figure 79 (Page 110):
We can see that, in 1R1T, DDR, FDD, LVDS config, the maximum data rate is half of DATA_CLK_P's rate, that is, 122.88 MSPS.
Another reference is from ad9361's no-OS api (no-OS/ad9361.c at 2015_R2 · analogdevicesinc/no-OS · GitHub) line 4330:
if (tx_sample_rate > (phy->pdata->rx2tx2 ? 61440000UL : 122880000UL))
The code tells me the max tx sample rate (same to rx sample rate) in 1R1T mode is 122.88 MSPS.
Jus in case, sample rate is for IQ combined, so 10 MSPS sampe rate means 480 Mbit/s data rate (12 for tx I, 12 for tx Q, 12 for rx I, 12 for rx Q), right?
I'm confused, ad9361's maximum sample data rate is 122.88 or 61.44 MSPS?