I must design a system with 4 chip AD9361 and I'm using FMCOMM5 as REFERENCE DESIGN.
The discrete In/Out (CNTRL_I , CNTRL_0, and others ) are connected to the GPIO(63..0) of CPU ( GPIO via EMIO).
When I use four chip AD9361 where can I interface the digital In and Out signal ?
The LIB IIO is configured to accept 4 channel ?
Can I use AXI_GPIO to connect digital IO between FPGA and AD9361 ?
Thanks in advance