I would use ADuM3480 and ADuM3481 to interface an FPGA (Xilinx Spartan 6) with a test board and our ASIC (under test) outputs.
The I/O lines from/to the FPGA includes, in example, two SPI channels (the first one to the test board devices, the second one to the ASIC), ASIC 5V CMOS digital outputs (input for the FPGA), etc.
The ASIC domain is a 5V (D5V_pcb) voltage domain with gnd_pcb ground.
The test board has two different domains: 3.3V (D3V3_pcb) and 5V (D5V_pcb) with a common ground reference gnd_pcb.
The FPGA domain is a 3.3V (D3V3_iso) with a separated ground reference gnd_fpga.
For both the devices ADuM3480 and ADuM3481, the following supplies configuration are required:
- VDD1 = 3.3V (D3V3_iso) GND1 = gnd_fpga (0V), VDD2 = 5V (D5V_pcb) GND2 = gnd_pcb (0V)
- VDD1 = 3.3V (D3V3_iso) GND1 = gnd_fpga (0V), VDD2 = 3.3V (D3V3_pcb) GND2 = gnd_pcb (0V)
- VDD1 = 5V (D5V_pcb) GND1 = gnd_pcb (0V), VDD2 = 3.3V (D3V3_iso) GND2 = gnd_fpga (0V)
Are the configuration above possible? Please confirm.
Any constraint about the VDD1 and VDD2 timing? Can VDD1 ramp-up before VDD2 and viceversa independently from the VDD1 and VDD2 values?
CTRL1 and CTRL2 set the default value for side 1 and side 2 respectively.
If VDD1 and VDD2 are 0V (at the start-up) the outputs of both sides are 0V.
If VDD1 is present and VDD2 = 0V the output at side 1 are at selected value (CTRL1) independently from the the indputs at side 2. Correct?
If VDD2 is present and VDD1 = 0V the output at side 2 are at selected value (CTRL2) independently from the the indputs at side 1. Correct?
If both the sides are powered, the outputs at side 1 reply the logic state at the corresponding inputs at side 2 and the outputs at side 2 reply the logic state at the corresponding inputs at side 1. Correct?
Does the logic state at the output terminals reply the logic state at the corresponding input terminals also in the case of static inputs?