AnsweredAssumed Answered

AD9361(FMCOMMS2) - no os - irregular I_clk clock ticks

Question asked by MiTfreak on Mar 10, 2016
Latest reply on Mar 25, 2016 by MiTfreak

Hi All,

 

 

I have been working with FMCOMMS1 for some time. Recently, I decided to port my HDL

design and to use FMCOMMS2 as RF front end. I searched the forum but did not find exact answer

on behavior that I observe. Below are details and questions.

 

- I used default NoOs project for FMCOMMS2 with these changes:

        1. I switched off one TxRx chain by changing from 1 to 0 //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable

        2. I set rf_bandwith for both Tx and Rx to 2MHz

        3. Frequency of local oscillator is set to 2.405 GHz

        4. I disabled FIR filters

        5. I set Rx sampling rate to 4Msps by using function ad9361_set_rx_sampling_freq

 

I need to clock my receiver core at 4 MHz. From what I understand from other discussions I_clk in 1TxRx mode is 2xSamplingRate.

When I use ILA to analyze samples that are coming from one of ADC channels (before fifo's) I see that they are coming in regular intervals. However, I_clk seems to have irregular clock ticks, seems that if samples are coming every 0.25us, that I_clk will have two clock ticks with periods of 0.12us and 0.13us.

 

Questions:

 

1. Is this normal behavior, or I made mistake in configuration of AD9361?

2. If I use different sampling rates for Tx (DAC) and Rx (ADC), what will I_clk represent? Which clk or clocks coming from AD9361 ip core should I use for clocking my custom Tx and Rx ip cores.

 

 

Kind Regards,

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