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how to configure ad9361 tx/rx sampling rate up to 100M?

Question asked by wanglixin on Mar 10, 2016
Latest reply on Mar 24, 2016 by wanglixin

Hi,

    We use AD9361 NO-OS software running on Airtex7-200t flatform. And there is a question confused me for a long time,I will be very appreciate if someone could help me!

     The issue is that I configure the ad9361 with 1R1T (or 2R2T )LVDS FDD mode and the digital interface tx sampling rate can running up to 61.44MHz,But I want configure the ad9361 with 1R1T LVDS FDD mode and the dampling rate 100MHz. It turn out that It initial failed or inital succeed but the captured adc data is wrong.

SAMPL CLK: 61440000 tuning: RX

  0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:

0:# # # # # # # # # # # # # # # #

1:# # # # # # # # # # # # # # # #

 

SAMPL CLK: 61440000 tuning: TX

  0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:

0:# # # # # # # # # # # # # # # #

1:# # # # # # # # # # # # # # # #

     although It could tune suceed ,the captured adc data is wrong!

     I am wondering if the AD9361 tx/rx sampling rate can running up to 100MHz? If it could be,how should I configure my board.

     By the way I used the LVDS_25(not support LVDS_18 in new version) IOSTANDARD but in fact the FPGA bank is connect to VCC 1.8V,may that inference the perfermance of the ad9361 digital interface?

Looking forward to hearing from you,thank you!

Best Regards

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