I’m using ADRF6720-EVALZ to achieve QPSK modulation. The baseband signal (BPRS, 100Mbps) generated by a BER tester is sent to an FPGA board, then it is converted to two parallel signals, namely I and Q signal. Both the differential signals (50MHz LVDS signal) are AC coupled to the ADRF6720-EVALZ and biased at 500 mV with resistor dividers from 3.3V power supply at the output ports of the FPGA board. The drive level tested on the ADRF6720-EVALZ is 700-800 mV p-p differential, 0 V offset.
Then the ADRF6720 is setup as the manual indicates. The internal LO is used with the 2XLO Path_INT_2X_VCO enabled. PLL and the output of the LO works well. However, the signal observed at the RF-output is just around 10 mV p-p. Check the MOD_EN or not makes no difference with the RF-output signal, also the presence of the baseband inputs. The current consumption is 330 mA with LO output driver enabled, and about 280 mA with LO output driver disabled.
1. Why is there nearly no signal at the RF-output? Is the reason that the differential swing of the baseband signal is smaller than 1 V p-p? Also, the DC bias is not exactly 500 mV.
2. Can the baseband inputs of the ADRF6720-EVALZ be used as single-ended signal? If it is possible, what’s the signal format and how to deal with the open port?